How do you design a glitch-free clock multiplexer?

Direct clock muxing causes glitches when switching between asynchronous clocks. Glitch-free design uses feedback to ensure clean transitions: Select change is synchronized to falling edge of current clock, output clock is gated off, then select is synchronized to new clock's falling edge before enabling. Implementation: Two synchronizers (one per clock), AND gates to gate each clock, OR gate to combine. Sequence ensures no clock is gating on when another might transition. Additional considerations: handle clock stopping, ensure minimum pulse width, and verify timing through simulation and STA. Some libraries provide dedicated glitch-free clock mux cells.