How is cache coherency managed in multi-core embedded systems?

Cache coherency ensures all cores see consistent memory values when caches contain copies of shared data. Problem: Core A writes to cached location; Core B's cache has stale copy. Coherency protocols: Snooping (bus-based): Caches monitor bus for writes to cached addresses. MESI protocol: Modified, Exclusive, Shared, Invalid states. Works well for smaller core counts. Directory-based: Central directory tracks cache line ownership. Scales better for many cores. Software considerations: Shared memory must handle coherency. DMA transfers may bypass cache (need flush/invalidate). Memory barriers ensure ordering. Cache maintenance operations: Invalidate (discard cached data). Clean (write back modified data). Flush (clean + invalidate). ARM cache maintenance: Data cache by virtual address (DCACHE), instruction cache considerations for code loading. Non-cacheable regions: Mark DMA buffers, device memory as non-cacheable or use cache maintenance.