How does ARM Cortex-M handle exceptions and what is the exception model?

Cortex-M uses a streamlined exception model: Exceptions include interrupts, faults, and system exceptions. Vector table at base of memory contains exception handler addresses. On exception: hardware automatically stacks registers (R0-R3, R12, LR, PC, PSR), loads PC from vector table, and switches to handler mode. NVIC prioritizes exceptions (lower number = higher priority). Tail-chaining optimizes consecutive exceptions. Late arrival allows higher priority exception to preempt in progress stacking. Exception return via special EXC_RETURN value in LR triggers unstacking.