How does interrupt priority and nesting work in microcontrollers?

Interrupt priority determines which interrupt is serviced first when multiple occur simultaneously. Higher priority interrupts can preempt (nest within) lower priority ISRs. In ARM Cortex-M, NVIC manages priorities with configurable levels (4-256). Priority inversion occurs when low-priority task blocks high-priority one; solutions include priority inheritance. Design considerations: minimize ISR time, avoid priority inversion, consider interrupt latency requirements. The 8051 has two priority levels; more advanced MCUs offer many levels and priority grouping.