What are advanced techniques for ultra-low-power embedded system design?

Ultra-low-power techniques: Sleep mode optimization (deepest sleep compatible with wake latency requirements), Dynamic voltage and frequency scaling (DVFS), Peripheral duty cycling (enable only when needed), Efficient wake sources (external interrupts, RTC, comparators), Event-driven architecture (avoid polling), DMA for data movement during CPU sleep, RAM retention selection (partial RAM power-down), Brownout detection configuration, and Voltage domain partitioning. Software considerations: Minimize active time, efficient algorithms, proper compiler optimization, and power-aware task scheduling. Measurement and profiling essential for optimization.