How do you optimize DSP algorithms for FPGA implementation?

FPGA DSP optimization: Parallelism (unroll loops, parallel filter sections, SIMD-like processing), Pipelining (insert registers for high clock rates, increases latency), Resource sharing (time-multiplex expensive operations like multipliers), Fixed-point optimization (minimize bit widths, saturating arithmetic), Memory architecture (block RAM vs distributed, ping-pong buffers), and DSP primitive utilization (MAC units in DSP48 blocks). Trade-offs: Throughput vs latency vs resources. High-level synthesis (HLS) helps, but manual optimization often needed for critical paths. Verification: bit-accurate simulation matching hardware.