How do you verify that a SIS design meets the required SIL?

SIL verification involves calculating PFDavg for the complete SIF and comparing to SIL targets. Process: obtain failure rate data from manufacturer safety manuals (lambda DU, lambda DD, lambda S), determine architecture contribution (voting configuration formulas), apply proof test interval (Ti affects dangerous undetected failure accumulation), account for diagnostic coverage, apply common cause beta factor for redundant elements, and calculate combined PFDavg for sensor + logic solver + final element subsystems. Verify: PFDavg meets SIL target, architectural constraints (SFF and fault tolerance) are met, and systematic capability of all components meets SIL. Use tools (exSILentia, SILver) or simplified equations.