How do you design the control loop for a switch-mode power supply?

SMPS control loop design requires modeling the power stage transfer function (depends on topology and operating mode), then designing compensator for stability and transient response. For voltage-mode buck in CCM: Power stage has LC double pole, ESR zero. Type III compensator provides two zeros (near LC resonance for phase boost) and three poles (at origin for DC accuracy, at ESR zero, and at half switching frequency). Current-mode control simplifies compensation by eliminating inductor pole. Design steps: Derive small-signal model, plot loop gain Bode plot, design compensator for target crossover frequency (typically 1/5 to 1/10 of fs) with adequate phase margin (>45 degrees), and verify transient response. Consider: RHP zero in boost/buck-boost, optocoupler dynamics in isolated supplies.