Analog Electronics Interview Questions

An amplifier is an electronic circuit that increases the amplitude of a signal without significantly altering its other characteristics. Key parameters include gain (ratio of output to input), bandwidth (frequency range of operation), input impedance (affects signal source loading), output impedance (affects load driving capability), and linearity (distortion characteristics).

BJT amplifiers are current-controlled devices with higher transconductance (gm), lower input impedance, and better linearity at low frequencies. MOSFET amplifiers are voltage-controlled with extremely high input impedance, lower power consumption, and better high-frequency performance. BJTs are preferred for low-noise applications while MOSFETs dominate in digital and high-impedance circuits.

An operational amplifier is a high-gain DC-coupled differential amplifier with single-ended output. Ideal characteristics include infinite open-loop gain, infinite input impedance, zero output impedance, infinite bandwidth, zero input offset voltage, and infinite common-mode rejection ratio (CMRR). Real op-amps approximate these ideals within specified limits.

In an inverting amplifier, the input signal is applied to the inverting terminal through a resistor, producing an output that is 180 degrees out of phase with gain -Rf/Rin. In a non-inverting amplifier, the input goes to the non-inverting terminal, producing an in-phase output with gain 1+Rf/Rin. Non-inverting has higher input impedance, while inverting offers virtual ground at the input.

Negative feedback is a technique where a portion of the output signal is fed back to the input in opposition to the input signal. Benefits include stabilized gain (less dependent on component variations), increased bandwidth, reduced distortion, improved input and output impedance characteristics, and reduced sensitivity to noise. The trade-off is reduced overall gain.

The common emitter (CE) amplifier has the emitter terminal common to both input and output circuits. It provides high voltage gain (typically 100-500), moderate current gain, 180-degree phase inversion between input and output, medium input impedance (1-5 kohm), and medium output impedance. It is the most widely used BJT amplifier configuration for general-purpose voltage amplification.

An oscillator is a circuit that generates a periodic waveform without an external input signal, converting DC power to AC. For sustained oscillation, the Barkhausen criteria must be met: the loop gain must be exactly unity (|A*beta| = 1), and the total phase shift around the loop must be 0 degrees or a multiple of 360 degrees. Common types include RC, LC, and crystal oscillators.

Main oscillator types include: RC oscillators (Wien bridge, phase shift) for audio frequencies with simple design; LC oscillators (Colpitts, Hartley, Clapp) for RF frequencies with good frequency stability; Crystal oscillators for high-precision frequency references in clocks and communication; and Relaxation oscillators (555 timer, astable multivibrator) for generating square waves and timing signals.

A voltage regulator maintains a constant output voltage despite variations in input voltage or load current. Main types are: Linear regulators (78xx series, LDOs) which dissipate excess voltage as heat with low noise but lower efficiency; Switching regulators (buck, boost, buck-boost) which use high-frequency switching for higher efficiency (85-95%) but with more noise and complexity.

CMRR is the ratio of differential-mode gain to common-mode gain in a differential amplifier, expressed in dB. It measures the ability to reject signals common to both inputs while amplifying the difference. High CMRR (typically 80-120 dB for op-amps) is crucial for rejecting noise and interference that appears equally on both input lines, essential in instrumentation and sensor applications.

A summing amplifier uses an op-amp in inverting configuration with multiple input resistors connected to the inverting terminal. The output is the inverted weighted sum of all inputs: Vout = -Rf(V1/R1 + V2/R2 + V3/R3...). When all input resistors are equal, it produces an inverted sum of inputs. It is used in audio mixers, digital-to-analog converters, and signal combining applications.

An integrator uses a capacitor in the feedback path and resistor at input, producing an output proportional to the integral of the input signal over time (Vout = -1/RC * integral of Vin). A differentiator uses a capacitor at input and resistor in feedback, producing output proportional to the rate of change of input (Vout = -RC * dVin/dt). Both are fundamental in analog computing and signal processing.

Class A amplifiers conduct for the full 360 degrees of input cycle, offering excellent linearity but only 25-30% efficiency. Class B amplifiers use two transistors each conducting for 180 degrees, achieving 78.5% theoretical efficiency but with crossover distortion. Class AB is a compromise where each transistor conducts for more than 180 degrees, reducing crossover distortion while maintaining reasonable efficiency (50-70%).

Passive filters use only resistors, capacitors, and inductors, requiring no external power and providing no gain but with limited frequency response flexibility. Active filters incorporate op-amps or transistors, providing gain, better selectivity, no inductors needed (important for IC integration), easier cascading without loading effects, and programmable characteristics. Active filters are preferred for precision applications below a few MHz.

A Zener diode operates in reverse breakdown region where it maintains a nearly constant voltage (Zener voltage) across it regardless of current variations within rated limits. In a simple regulator circuit, the Zener is connected in parallel with the load through a series resistor. When input voltage increases, the Zener conducts more current while maintaining constant output voltage. It is simple but suitable only for low-power applications due to power dissipation.

Slew rate is the maximum rate of change of output voltage (V/us), limiting large-signal high-frequency response. If input changes faster than slew rate allows, output distorts. Gain-bandwidth product (GBW) is constant for a given op-amp; as gain increases, bandwidth decreases proportionally. For a 1MHz GBW op-amp at gain of 10, bandwidth is 100kHz. Both parameters must be considered when selecting op-amps for high-speed or high-amplitude applications.

A BJT differential pair uses two matched transistors with emitters connected to a common current source. Differential input is applied between bases, and output is taken differentially or single-ended. CMRR depends on: tail current source impedance (higher is better), transistor matching, resistor matching, and temperature stability. Using a current mirror as tail current source instead of a resistor dramatically improves CMRR from 40-60dB to over 80dB.

A cascode amplifier stacks a common-emitter (or common-source) stage with a common-base (or common-gate) stage. Advantages include: very high output impedance (product of individual output impedances), improved high-frequency response by reducing Miller effect, higher voltage gain, and better isolation between input and output. It is widely used in RF amplifiers, current sources, and high-gain stages where bandwidth and output impedance are critical.

The Colpitts oscillator uses an LC tank circuit with two capacitors (C1, C2) in series and an inductor (L) in parallel for frequency determination. The transistor provides gain and the capacitive divider provides feedback. Oscillation frequency is f = 1/(2*pi*sqrt(L*Ceq)) where Ceq = C1*C2/(C1+C2). The feedback factor beta = C1/C2, so C2 > C1 for proper feedback. Start-up requires loop gain > 1, typically achieved with gm*R > C1/C2.

An instrumentation amplifier is a precision differential amplifier with three op-amps providing high input impedance on both inputs, high CMRR (>100dB), adjustable gain with single resistor, and low offset drift. The standard topology uses two input buffers and one differential stage. It is preferred for sensors because it can accurately amplify small differential signals (mV range from strain gauges, thermocouples) while rejecting large common-mode signals from ground loops and interference.

A basic current mirror uses two matched transistors; one is diode-connected (reference) and sets the current, the other mirrors this current to the output. For BJTs: Iout = Iref * (1 + 1/beta), with output impedance ro. Improved topologies include: Wilson current mirror (higher output impedance, reduced beta error), Cascode current mirror (very high output impedance for precision applications), and Widlar current mirror (for generating small currents from larger references using emitter resistor).

A PLL is a feedback system that synchronizes an output signal with a reference signal in both frequency and phase. Components include: Phase detector (compares reference and feedback phases), Loop filter (converts phase error to control voltage, determines dynamics), VCO (generates output frequency proportional to control voltage), and Frequency divider (in feedback for frequency multiplication). PLLs are used in frequency synthesis, clock recovery, FM demodulation, and motor speed control.

Key LDO considerations include: Dropout voltage (minimum Vin-Vout for regulation, typically 100-500mV), Quiescent current (affects battery life in portable devices), Load regulation (output change vs load current), Line regulation (output change vs input voltage), PSRR (power supply rejection ratio for noise immunity), Transient response (stability with varying loads), and Output capacitor requirements (ESR affects stability). Trade-offs exist between dropout, quiescent current, and transient response.

A second-order Butterworth filter has maximally flat passband response with -40dB/decade rolloff. Using Sallen-Key topology: Choose cutoff frequency fc, select C1 = C2 = C for simplicity, calculate R = 1/(2*pi*fc*C). For Butterworth response, Q = 0.707, requiring gain K = 3 - 1/Q = 1.586 for unity-gain stable filter. Components Rf and Rin set the gain. The Butterworth polynomial coefficients determine the exact damping ratio for flat response. Multiple sections can be cascaded for higher order.

Common MOSFET biasing techniques include: Fixed bias (simple but unstable with Vth variations), Self-bias with source resistor (provides negative feedback for stability), Voltage divider bias (sets stable gate voltage, source resistor for further stability), and Current source biasing (best for IC design with current mirrors). For MOSFETs, the goal is to set proper ID and VDS for desired gm while ensuring operation in saturation region. Source degeneration resistor helps stabilize operating point against threshold voltage variations.

Thermal noise (Johnson-Nyquist) is generated by random thermal motion of charge carriers in resistive elements: Vn = sqrt(4kTRB) where k is Boltzmann constant, T is temperature, R is resistance, B is bandwidth. Shot noise occurs due to discrete nature of charge carriers in semiconductor junctions: In = sqrt(2qIB) where q is electron charge and I is DC current. Both are white noise (flat spectrum). Minimizing noise requires low-impedance design, cooling, proper bandwidth limiting, and selection of low-noise components.

A buck converter steps down voltage using a switch (MOSFET), diode (or synchronous MOSFET), inductor, and capacitor. During switch ON, inductor current rises as energy is stored; during OFF, inductor releases energy through the diode. Key equations: Duty cycle D = Vout/Vin, Inductor L = (Vout*(1-D))/(fs*delta_IL) where delta_IL is ripple current, Output capacitor C = delta_IL/(8*fs*delta_Vout). Continuous conduction mode requires minimum load current. Efficiency can exceed 95% with proper design.

Crystal oscillators use piezoelectric quartz resonators providing excellent frequency stability (1-100 ppm typical, 0.1 ppm for TCXO). Key specifications include: Frequency tolerance (initial accuracy), Temperature stability (variation over temperature range), Aging (long-term drift, typically 1-5 ppm/year), Phase noise (affects signal purity), and Load capacitance (must match circuit for accurate frequency). Operating modes include fundamental and overtone. Pierce, Colpitts, and Butler configurations are common crystal oscillator circuits.

While both are differential input devices, comparators are optimized for open-loop operation with fast response time (ns range), rail-to-rail output swing for digital compatibility, and no frequency compensation (would slow response). Op-amps are designed for closed-loop operation with internal compensation for stability, linear output range, and lower speed. Using an op-amp as comparator results in slow response and possible oscillation; using a comparator in linear mode causes instability.

Class D amplifiers use pulse-width modulation (PWM) to switch output transistors fully ON or OFF, theoretically achieving 100% efficiency (practically 90-95%). The audio signal modulates the duty cycle of a high-frequency carrier (typically 400kHz-1MHz). A low-pass filter reconstructs the analog signal at the output. Advantages include high efficiency (minimal heat, smaller heatsinks), compact size, and lower power supply requirements. Challenges include EMI, output filter design, and maintaining THD comparable to linear amplifiers.

Input offset voltage (Vos) results from mismatches in the differential input stage transistors, including threshold voltage differences, geometry variations, and temperature gradients. Compensation methods include: Internal nulling using offset trim pins with external potentiometer, Auto-zero techniques (chopper stabilization, correlated double sampling) achieving sub-microvolt offsets, External circuit compensation using offset adjustment resistors, and Selecting precision op-amps with laser-trimmed inputs. For high-precision applications, also consider offset drift with temperature (typically 1-10 uV/C).

A transimpedance amplifier (TIA) converts photodiode current to voltage using an op-amp with feedback resistor Rf. Output Vout = Iph * Rf. Key design considerations: Bandwidth is limited by op-amp GBW and photodiode capacitance Cd (f-3dB = sqrt(GBW/(2*pi*Rf*Cd))), Stability requires feedback capacitor Cf = sqrt(Cd/(2*pi*Rf*GBW)), Noise is dominated by Rf thermal noise and op-amp current noise. Trade-offs exist between gain (Rf), bandwidth, and noise. FET-input op-amps preferred for low current noise.

Voltage reference types include: Bandgap references (1.25V typical, using silicon bandgap voltage, temperature-compensated), Zener references (higher voltage, lower precision), and Buried Zener (premium precision). Key specifications are: Initial accuracy (0.02% to 2%), Temperature coefficient (1-100 ppm/C), Long-term stability (drift over years), Noise (affects ADC performance), Line regulation, and Load regulation. For precision applications, choose bandgap references with curvature compensation achieving <10 ppm/C, and consider thermal hysteresis effects.

A Schmitt trigger is a comparator with positive feedback creating hysteresis, two different threshold voltages for rising and falling inputs. This prevents output oscillation from noisy inputs. Using an op-amp with positive feedback: Upper threshold VTH = Vref * (1 + R1/R2), Lower threshold VTL = Vref * (1 - R1/R2). Hysteresis width = VTH - VTL = 2*Vref*R1/R2. Non-inverting configuration provides wider hysteresis range. Schmitt triggers are essential for cleaning up noisy signals and in oscillator circuits.

Multistage amplifier design involves cascading stages to achieve desired gain, bandwidth, and impedance matching. Analysis considers: Individual stage gains multiply for overall gain (in dB, they add), Bandwidth typically decreases as stages are added (for n identical stages, BW = BW1 * sqrt(2^(1/n) - 1)), Input impedance determined by first stage, output impedance by last stage, and Interstage coupling (DC coupling preserves low-frequency response, AC coupling blocks DC but adds poles). Design proceeds from output to input, considering load requirements first, then working back to source requirements.

A fully differential amplifier has differential inputs and outputs, offering better noise immunity, doubled output swing, and even-harmonic cancellation. However, without common-mode feedback (CMFB), the output common-mode voltage is undefined. CMFB circuit senses output common-mode level (using resistive averaging or switched-capacitor sensing), compares to reference, and adjusts a current source in the amplifier. Design considerations include CMFB bandwidth (must be higher than main amplifier bandwidth for stability), settling time, and loop gain. CMFB adds complexity but is essential for proper operation.

Sigma-delta modulators use oversampling and noise shaping to achieve high resolution with simple comparators. The integrator accumulates the difference between input and quantizer output, pushing quantization noise to higher frequencies where it is filtered. Design considerations include: Oversampling ratio (higher gives more resolution but requires faster clock), Loop order (higher order provides more aggressive noise shaping but stability becomes critical), Quantizer levels (multi-bit improves SNR but requires DAC linearity), Integrator topology (affects stability and SNR), and Digital decimation filter design. A second-order modulator achieves approximately 15-bit resolution at 64x oversampling.

LNA design requires balancing noise figure (NF), gain, linearity (IIP3), power consumption, and input matching. Noise optimization: Select optimal source impedance (Zopt, not necessarily 50 ohm), use inductive source degeneration for simultaneous noise and impedance matching, minimize parasitic resistances, and choose appropriate bias current. Linearity optimization: Higher bias improves IIP3 but increases power, use negative feedback carefully (helps linearity but may degrade NF), and optimize transistor size. Trade-offs: NF and IIP3 often conflict; use cascaded stages with high-linearity second stage. Simulate S-parameters, NF, and IP3 across frequency and temperature.

PLL loop dynamics are analyzed using linearized s-domain model: Phase detector gain Kpd (V/rad), VCO gain Kvco (rad/s/V), divider ratio N, and loop filter transfer function F(s). Open-loop gain = Kpd*Kvco*F(s)/N. Design goals: Phase margin > 60 degrees for stability, Loop bandwidth (typically 1/10 to 1/20 of reference frequency) trades off lock time vs phase noise, Damping factor around 0.707 for critical damping. For charge-pump PLL, second-order filter with series R-C creates a zero for phase margin; third-order adds pole to reduce reference spurs. Phase noise analysis requires considering VCO noise, reference noise, and loop bandwidth effects.

An OTA outputs current proportional to differential input voltage, with transconductance (gm) controllable via bias current. Key characteristics: gm = Ibias/(2*VT) for BJT, Output is high-impedance current source, Gain is gm*Rload. IC applications include: Gm-C filters (OTA + capacitor creates integrator, tunable by bias current), Voltage-controlled amplifiers, PLL loop filters, and Continuous-time sigma-delta modulators. Design considerations include linearity (limited input range before gm degradation), noise (proportional to sqrt(gm)), and power-bandwidth trade-off. Linearization techniques include source degeneration and cross-coupled differential pairs.

High-efficiency PA design involves selecting appropriate class based on application. Class AB provides moderate efficiency (50-60%) with good linearity for variable-envelope signals. Class C offers higher efficiency (70-80%) for constant-envelope FM/PM signals but poor linearity. Switching classes (D, E, F) achieve theoretical 100% by operating transistors as switches. Class E uses optimized load network for zero-voltage switching at turn-on. Class F uses harmonic tuning with open/short at harmonics. For modern wireless (OFDM), efficiency enhancement techniques include: Envelope tracking (dynamic supply modulation), Doherty combining (efficiency back-off improvement), and Digital pre-distortion (linearize efficient but nonlinear PAs).

VCO phase noise is characterized by Leeson's equation: L(fm) = (F*kT/(2*Ps)) * (1 + (fo/(2*Q*fm))^2) * (1 + fc/fm), where fm is offset frequency, fo is carrier frequency, Q is tank quality factor, Ps is signal power, F is device noise factor, and fc is flicker noise corner. Minimization strategies: Maximize Q (use high-Q inductors, minimize varactor losses), Increase signal amplitude (limited by supply and reliability), Reduce flicker noise (larger transistors, optimized bias), Use filtering of bias noise, and Choose optimal coupling factor in oscillator. Differential LC-VCOs reduce common-mode noise. Tail current noise filtering with inductor or capacitor helps at low offsets.

Basic bandgap combines PTAT (proportional to absolute temperature) voltage from delta-VBE of two transistors at different current densities with CTAT (complementary to absolute temperature) VBE. Reference Vref = VBE + K*delta_VBE where K is chosen to cancel first-order temperature dependence, yielding approximately 1.25V (silicon bandgap). Curvature compensation addresses higher-order terms: Techniques include adding nonlinear current source (exponential or squared PTAT), using beta-compensated VBE subtraction, implementing piecewise-linear correction, or employing trimmed resistor ratios. Advanced designs achieve < 5ppm/C temperature coefficient. Also address: supply rejection, noise, and start-up circuits.

Switched-capacitor (SC) circuits use capacitors and switches (clocked MOSFETs) to emulate resistors: R_eq = 1/(f_clk * C). Advantages include precise ratios (capacitor matching > resistor matching in ICs), tunability via clock frequency, and no continuous power dissipation in equivalent resistance. Design considerations: Clock feedthrough (charge injection from switches, mitigate with complementary switches, bottom-plate sampling), Finite op-amp gain (causes gain error), Op-amp settling time (must settle within clock phase), kT/C noise (limits minimum capacitor size: noise = kT/C), and Non-overlapping clock generation. SC filters and ADCs are ubiquitous in mixed-signal ICs.

Successive Approximation Register (SAR) ADC uses binary search algorithm with DAC and comparator. Each clock cycle determines one bit, requiring N cycles for N bits. Key components: Capacitor DAC (binary-weighted or segmented), Comparator (speed and offset critical), Sample-and-hold (bootstrapped switches for linearity), and SAR logic. High-speed design considerations: Comparator regeneration time sets speed limit, DAC settling must complete within bit cycle, Reference buffer must source transient currents, Capacitor mismatch limits linearity (calibration needed beyond 10-12 bits). Architecture improvements: Redundancy for comparator errors, time-interleaving for higher throughput, and asynchronous timing. SAR ADCs excel in power efficiency at 8-16 bit resolution.

Two-stage op-amps have two high-gain poles, requiring compensation for stability. Miller compensation places capacitor (Cc) between first stage output and second stage output, creating dominant pole p1 = 1/(Av2*Cc*Rout1) and pushing second pole higher. Unity-gain bandwidth GBW = gm1/(Cc). Right-half-plane zero at gm2/Cc causes phase lag; nulling resistor Rz = 1/gm2 places zero at infinity, or Rz > 1/gm2 creates LHP zero for phase lead. Design procedure: Choose Cc for desired phase margin (typically 60 degrees), size Rz to null RHP zero, ensure non-dominant poles are at least 2-3x GBW. Also consider: load capacitance effects, power-bandwidth trade-offs, and multi-path feedforward for improved slewing.

Current-mode circuits process signals as currents rather than voltages. Advantages: Higher bandwidth (no need to charge node capacitances to specific voltages), Better linearity in some topologies, Lower supply voltage operation (signals not limited by voltage swing), and Natural implementation of mathematical operations (Kirchhoff current law). Examples: Current conveyors, log-domain filters (compress dynamic range using exponential I-V of transistors), translinear circuits. Challenges include: Higher noise (current noise sources), More sensitive to leakage, and Less intuitive design. Current-mode is particularly useful in high-frequency, low-power, and log-domain filtering applications.

Chopper amplifiers modulate the input signal to higher frequency, amplify it (where 1/f noise and offset are negligible), then demodulate back. The DC offset and 1/f noise of the amplifier are modulated to chopping frequency and filtered out. Result: microvolt-level offset, sub-nV/sqrt(Hz) noise at DC. Design challenges: Charge injection from chopping switches creates residual offset, Intermodulation of signals near chopping frequency, Settling time requirements during chopping transients, Input impedance modulation at chopping frequency, and High-frequency noise folding to baseband. Solutions include nested chopping, auto-zeroing combined with chopping, and careful switch design with dummy transistors.

SMPS control loop design requires modeling the power stage transfer function (depends on topology and operating mode), then designing compensator for stability and transient response. For voltage-mode buck in CCM: Power stage has LC double pole, ESR zero. Type III compensator provides two zeros (near LC resonance for phase boost) and three poles (at origin for DC accuracy, at ESR zero, and at half switching frequency). Current-mode control simplifies compensation by eliminating inductor pole. Design steps: Derive small-signal model, plot loop gain Bode plot, design compensator for target crossover frequency (typically 1/5 to 1/10 of fs) with adequate phase margin (>45 degrees), and verify transient response. Consider: RHP zero in boost/buck-boost, optocoupler dynamics in isolated supplies.

RF mixers perform frequency translation by multiplying RF and LO signals. Passive mixers (diode ring, passive FET) have conversion loss but excellent linearity (IP3 can exceed +30dBm), requiring high LO drive. Active mixers (Gilbert cell) provide conversion gain but lower linearity. Noise figure depends on conversion loss/gain and device noise contributions. Linearity analysis: Third-order products from RF nonlinearity set IIP3. Improvement techniques: LO signal optimization (fast switching reduces LO-feedthrough), Biasing for linearity (higher current improves IP3), Degeneration resistors, and Current-bleeding. Trade-offs exist between conversion gain, noise figure, linearity, and power consumption. Modern designs use complementary switching for flicker noise reduction.