Explain SAR ADC architecture and design considerations for high-speed applications.

Successive Approximation Register (SAR) ADC uses binary search algorithm with DAC and comparator. Each clock cycle determines one bit, requiring N cycles for N bits. Key components: Capacitor DAC (binary-weighted or segmented), Comparator (speed and offset critical), Sample-and-hold (bootstrapped switches for linearity), and SAR logic. High-speed design considerations: Comparator regeneration time sets speed limit, DAC settling must complete within bit cycle, Reference buffer must source transient currents, Capacitor mismatch limits linearity (calibration needed beyond 10-12 bits). Architecture improvements: Redundancy for comparator errors, time-interleaving for higher throughput, and asynchronous timing. SAR ADCs excel in power efficiency at 8-16 bit resolution.