How do you design frequency compensation for a two-stage op-amp?

Two-stage op-amps have two high-gain poles, requiring compensation for stability. Miller compensation places capacitor (Cc) between first stage output and second stage output, creating dominant pole p1 = 1/(Av2*Cc*Rout1) and pushing second pole higher. Unity-gain bandwidth GBW = gm1/(Cc). Right-half-plane zero at gm2/Cc causes phase lag; nulling resistor Rz = 1/gm2 places zero at infinity, or Rz > 1/gm2 creates LHP zero for phase lead. Design procedure: Choose Cc for desired phase margin (typically 60 degrees), size Rz to null RHP zero, ensure non-dominant poles are at least 2-3x GBW. Also consider: load capacitance effects, power-bandwidth trade-offs, and multi-path feedforward for improved slewing.