How do you design an asynchronous FIFO for clock domain crossing?

Asynchronous FIFO design requires: Dual-port RAM accessed by write (clk_wr) and read (clk_rd) domains independently, Gray-coded write and read pointers (single-bit changes for safe synchronization), Pointer synchronization using 2-stage synchronizers to opposite clock domain, and Full/empty flag generation comparing synchronized pointers. Full condition: write pointer equals synchronized read pointer after increment. Empty condition: read pointer equals synchronized write pointer. Gray code ensures no multi-bit transitions during synchronization. FIFO depth must be power of 2 for proper Gray code rollover. Design must handle potential metastability in synchronizers.