What is scan chain design for testability and how is it implemented?

Scan design converts flip-flops to scan flip-flops with multiplexed inputs: normal mode uses functional data, scan mode uses serial shift path. During testing: 1) Shift in test pattern through scan chain, 2) Apply one clock in functional mode, 3) Shift out responses for comparison. Implementation considerations: Scan chain length (affects test time), number of chains (parallel patterns), scan enable timing (must not create hold violations), and compression techniques (reduce IO pins needed). Scan insertion is automatic in modern synthesis tools. ATPG tools generate test patterns achieving high fault coverage (>95% typically required).