What is formal verification and how does it complement simulation?

Formal verification mathematically proves or disproves properties without simulation. Techniques include: Model checking (exhaustively verify properties against state space), Equivalence checking (prove two designs functionally identical), and Theorem proving (mathematical proofs for complex properties). Advantages: exhaustive coverage, finds corner cases, verifies RTL-to-gate equivalence. Limitations: state space explosion for large designs, property specification challenges, and may not find all bugs if properties incomplete. Modern methodology combines formal for control-intensive blocks and specific properties with simulation for data-intensive and system-level verification.