What are the key techniques for low-power digital design?

Low-power techniques address dynamic power (P = alpha*C*V^2*f) and static/leakage power. Dynamic: Clock gating (eliminate switching in idle blocks), Operand isolation (gate data to unused units), Multi-Vdd (lower voltage for non-critical paths), and DVFS (dynamic voltage and frequency scaling). Leakage: Multi-Vt (high-Vt for non-critical paths), Power gating (switch off unused blocks), and State retention power gating. Architecture level: Minimize switching activity, efficient coding, memory optimization. Verification requires power-aware simulation tracking switching activity and leakage states.