Explain the fundamentals of static timing analysis for digital circuits.

STA verifies timing without simulation by analyzing all paths. Key concepts: Setup check ensures data arrives before clock edge: Data_arrival < Clock_arrival + T_period - T_setup. Hold check ensures data stable after clock edge: Data_arrival > Clock_arrival + T_hold. Critical path is longest combinational delay determining maximum frequency. Analysis includes: clock network delays, clock uncertainty (jitter, skew), multi-cycle paths, false paths, and operating conditions (PVT corners). STA tools report slack (positive = met, negative = violated), worst negative slack (WNS), and total negative slack (TNS) for design qualification.