How do you design memory Built-In Self-Test (BIST)?

Memory BIST tests embedded memories using on-chip test logic. Components: Pattern generator (creates address/data patterns like march algorithms), Address generator (provides memory addresses in required sequence), Response analyzer (compares read data with expected), and BIST controller (sequences test operations). Common algorithms: March C- (11n operations, detects coupling faults), MATS+ (simple, detects stuck-at), checkerboard (detects pattern-sensitive faults). Implementation considerations: Area overhead (typically 3-5%), test time, fault coverage, and diagnosis capability. At-speed testing requires careful clock domain management between BIST and functional clocks.