What are the principles and trade-offs in designing pipelined digital systems?

Pipelining inserts registers to divide combinational logic into stages, increasing throughput at cost of latency. Design principles: Balance stage delays (unbalanced stages limit frequency to slowest), minimize pipeline overhead (register setup/hold, clock-to-Q), and handle data dependencies (forwarding, stalling, speculation). Trade-offs: More stages = higher frequency but more latency, area, and power; diminishing returns as overhead dominates. Control hazards require branch prediction or pipeline flushing. Data hazards need forwarding paths. Retiming tools can automatically optimize pipeline register placement. Throughput = frequency, latency = stages x period.