How do you design a power-optimized state machine?

Power-optimized FSM techniques: Encoding selection (Gray encoding minimizes bit transitions between adjacent states), clock gating (disable clock when state is stable and no inputs change), state assignment (assign frequently visited states to minimize transitions), and power gating for rarely used states. Analysis requires: state transition probability estimation, encoding evaluation for switching activity, and power simulation. Advanced techniques: decompose FSM into active/idle portions, use one-hot for glitch reduction in FPGA, and optimize reset state location. Trade-offs exist between encoding for power, area, and timing.