What factors affect interrupt latency and how can it be minimized?

Interrupt latency is the time from interrupt request to start of ISR execution. Contributing factors: Interrupt recognition time (processor cycles to detect). Context save time (push registers to stack). Pipeline flush on branch to ISR. Bus arbitration delays. Higher priority interrupt handling. Critical sections disabling interrupts. Memory access time for ISR code. Minimization techniques: Keep critical sections short. Use fast interrupt vectors (ARM Cortex-M NVIC). Enable interrupt nesting with proper priorities. Place ISR code in fast memory (TCM, cache). Use tail-chaining (skip context save/restore between ISRs). Minimize ISR work (defer to task via semaphore). Use DMA for data movement. Profile with oscilloscope or trace tools. Typical Cortex-M4: 12 cycles minimum, practical 100s of ns to few us.