How do you optimize cache utilization in embedded processors?

Cache optimization techniques: Data structure layout (avoid cache line conflicts, align to cache lines), Loop optimization (tiling for cache blocking, loop interchange for spatial locality), Prefetching (software hints or hardware prefetcher), Code placement (hot paths together, cold paths separate), Data placement (frequently used data in cache-friendly regions), Cache locking (critical data/code locked in cache for determinism), and Cache partitioning (way-based partitioning for isolation). Analysis: Cache miss profiling, conflict analysis, working set size calculation. Real-time considerations: Disable cache for determinism or analyze WCET with cache effects. Instruction cache vs data cache optimization may require different strategies.