Explain clock gating techniques for power reduction.

Clock gating disables clock to idle flip-flops, eliminating switching power. Types: Latch-based (ICG - Integrated Clock Gating cell uses latch to avoid glitches), Latch-free (AND/OR gate, prone to glitches). Implementation: Synthesis tool identifies enable conditions, inserts gating cells, merges gates for efficiency. Considerations: Setup/hold timing of enable signal, gating cell latency, sequential clock gating (multi-cycle enable), and verification of clock gating coverage. Typical savings: 20-40% dynamic power. Clock gating is essential for low-power design alongside multi-Vt and power gating.