VLSI Design Interview Questions

VLSI (Very Large Scale Integration) refers to integrating millions to billions of transistors on a single chip. It enables complex systems like microprocessors, memory, and SoCs in small, low-power, and cost-effective packages. VLSI follows Moore's Law, doubling transistor density approximately every two years. This has enabled the revolution in computing, mobile devices, and IoT. Modern VLSI involves sophisticated design automation tools, advanced manufacturing processes (7nm, 5nm, 3nm nodes), and multidisciplinary expertise.

NMOS (N-channel MOSFET) uses electrons as carriers, has n-type source/drain in p-type substrate, turns on with positive gate voltage (Vgs > Vth), and passes strong 0 but weak 1. PMOS (P-channel MOSFET) uses holes as carriers, has p-type source/drain in n-well, turns on with negative gate voltage (Vgs < Vth), and passes strong 1 but weak 0. NMOS is faster (higher electron mobility) but both are combined in CMOS for complementary operation with low static power.

A CMOS inverter consists of PMOS (connected to VDD) and NMOS (connected to GND) with gates tied together. When input is low (0), PMOS is on, NMOS is off, output is pulled to VDD (1). When input is high (1), NMOS is on, PMOS is off, output is pulled to GND (0). At no time are both transistors fully on, minimizing static power consumption. The switching threshold is ideally at VDD/2 for symmetric transistors. CMOS inverter is the fundamental building block of all digital CMOS circuits.

Dynamic power is consumed during switching: P_dyn = alpha * C * V^2 * f, where alpha is activity factor, C is load capacitance, V is supply voltage, and f is frequency. It dominates in older technologies. Static power (leakage) flows when circuits are idle, mainly from subthreshold leakage, gate leakage, and junction leakage. It becomes significant in advanced nodes (below 90nm). Total power = dynamic + static. Modern low-power design addresses both through techniques like clock gating (dynamic) and power gating (static).

Threshold voltage (Vth) is the minimum gate-to-source voltage required to create a conducting channel between source and drain. Below Vth, the transistor is in subthreshold region with exponentially decreasing current. Above Vth, strong inversion occurs and transistor conducts normally. Vth depends on oxide thickness, doping levels, body bias, and temperature. Multi-threshold CMOS (MTCMOS) uses high-Vth transistors for low leakage in non-critical paths and low-Vth for high speed in critical paths.

RTL (Register Transfer Level) design flow: 1) Specification - define functionality, 2) RTL coding - write Verilog/VHDL describing registers and combinational logic, 3) Functional verification - simulate to verify correctness, 4) Synthesis - convert RTL to gate-level netlist, 5) Static timing analysis - verify timing requirements, 6) Physical design - place and route, 7) Sign-off verification - final timing, power, DRC/LVS checks. This flow transforms behavioral description to manufacturable layout through automated tools while ensuring functional and timing correctness.

Setup time (Tsu) is the minimum time data must be stable before the clock edge for reliable capture. Hold time (Th) is the minimum time data must remain stable after the clock edge. Violating setup time causes incorrect data capture; violating hold time causes the new data to corrupt the just-captured value. These timing constraints arise from flip-flop internal structure (propagation through latches). Static timing analysis verifies all paths meet setup and hold requirements under worst-case conditions (PVT corners).

Fan-in is the number of inputs a logic gate can accept. High fan-in increases gate delay due to series transistors (NMOS in NAND, PMOS in NOR) and internal capacitance. Fan-out is the number of gates a single output can drive. High fan-out increases load capacitance, slowing down the driving gate. Fan-out is limited by the drive strength of the output buffer. Design must balance fan-in (typically 4 or less) and fan-out (inserting buffers when needed) for optimal timing.

Combinational circuits have outputs depending only on current inputs with no memory elements. Examples: adders, multiplexers, decoders. They create combinational paths between flip-flops. Sequential circuits include memory elements (flip-flops, latches) and outputs depend on inputs and current state. They implement state machines and registers. In timing analysis, combinational delay determines setup slack; sequential elements define clock boundaries. Both are essential: sequential for state storage, combinational for data processing between states.

Logic synthesis transforms RTL description (Verilog/VHDL) into gate-level netlist using cells from a technology library. The synthesizer optimizes for area, timing, and power while meeting constraints. Steps: RTL parsing, technology-independent optimization (Boolean minimization, common subexpression elimination), technology mapping (mapping to library cells), and timing optimization (buffer insertion, cell sizing). Key inputs: RTL code, constraints (clock, I/O timing), and technology library. Output: Netlist in standard format (Verilog, DEF). Modern tools: Synopsys Design Compiler, Cadence Genus.

A standard cell library contains pre-designed, pre-characterized logic cells (inverters, NAND, NOR, flip-flops, etc.) with fixed height and variable width. Each cell includes: Layout (transistors, routing), Timing models (delay, transition, constraints), Power models (dynamic, leakage), and Abstract views for place-and-route. Cells are characterized across PVT (Process, Voltage, Temperature) corners. Modern libraries have hundreds to thousands of cells with multiple drive strengths, threshold voltages, and functionality. Libraries are foundry-specific and technology-node-specific.

Floorplanning is the first step in physical design, defining chip organization. It involves: Placing hard macros (memories, IPs) and soft blocks, Defining power grid structure, Creating placement blockages, Planning I/O and pin locations, and Establishing power domains. Good floorplanning minimizes wirelength, congestion, and timing issues. Considerations include: data flow (related blocks close together), power distribution, clock tree planning, and manufacturing constraints. Iterative process with early timing estimates guiding decisions.

DRC (Design Rule Check) verifies that layout geometry meets manufacturing constraints: minimum width, spacing, enclosure, and area rules. Violations cause manufacturing defects. LVS (Layout Versus Schematic) verifies that layout correctly implements the intended circuit by extracting devices and connections from layout and comparing to schematic netlist. Both are essential sign-off checks before tape-out. Tools: Calibre, IC Validator, PVS. Clean DRC and LVS are mandatory for fabrication.

Clock tree synthesis builds the clock distribution network from clock source to all sequential elements (flip-flops). Goals: minimize skew (variation in clock arrival times), achieve target latency, meet transition time constraints, and minimize power. CTS inserts clock buffers and inverters in a tree or mesh structure. Balanced trees reduce skew; useful skew can improve timing. Modern CTS considers: OCV (on-chip variation), concurrent clock-data optimization, and multi-mode multi-corner (MMMC) analysis. CTS significantly impacts timing closure and power.

Verilog is a hardware description language (HDL) for modeling digital circuits at multiple abstraction levels: behavioral (algorithms), RTL (register transfers), and gate-level (structural). Key constructs: modules (design units), always blocks (sequential/combinational logic), assign statements (continuous assignments), and wire/reg data types. Uses include: RTL design (synthesizable code), testbench development (simulation), gate-level simulation, and formal verification. SystemVerilog extends Verilog with advanced verification features (classes, assertions, coverage).

Timing closure techniques: Gate sizing (upsize critical path cells, downsize non-critical for area), Buffer insertion (reduce load, manage slew), Logic restructuring (parallelize logic, reduce depth), Useful skew (intentionally skew clock to borrow time), Layer assignment (fast metal layers for critical nets), Placement optimization (move cells closer), and VT swapping (low-Vt for critical paths). Process involves iterative refinement, using timing reports to identify violations and applying incremental fixes. ECO (Engineering Change Order) enables late-stage targeted fixes.

CDC handling involves: Synchronizers (2FF for single-bit, multi-bit needs special treatment), Gray coding (for counters crossing domains), Asynchronous FIFOs (for data transfers), Handshake protocols (request/acknowledge), and Pulse synchronizers (for single-cycle signals). Verification: CDC analysis tools (Spyglass CDC, Conformal) detect missing synchronizers, reconvergence issues, and multi-bit signal problems. Design guidelines: minimize CDC signals, use established crossing circuits, document intentional exceptions, and verify MTBF requirements. Metastability is inherent; synchronizers reduce failure probability to acceptable levels.

Corners represent PVT (Process, Voltage, Temperature) variations: SS (slow-slow, worst setup), FF (fast-fast, worst hold), typical, and various combinations. OCV (on-chip variation) adds local variations. Modes represent functional configurations: different clock frequencies, power states, or test modes. MMMC (Multi-Mode Multi-Corner) analysis runs STA across all relevant mode-corner combinations. Typically: setup checked at slow corners (worst-case delays), hold checked at fast corners (minimum delays). Signoff may require passing 10-30+ scenarios covering operating conditions.

Power gating switches off unused blocks to eliminate leakage. Implementation: Sleep transistors (high-Vt PMOS headers or NMOS footers) connect block to supply, Isolation cells prevent floating outputs from corrupting always-on logic, Retention flip-flops save state before power-down, Level shifters handle voltage differences, and Power control unit sequences on/off events. Design considerations: rush current during wake-up (inrush), wake-up latency, area overhead (10-15%), and IR drop through sleep transistors. Coarse-grained (full blocks) is simpler; fine-grained adds overhead but more flexibility.

Parasitic extraction computes resistance (R) and capacitance (C) values from physical layout geometry for accurate timing, power, and signal integrity analysis. Extracts: Wire resistance (length, width, sheet resistance), Coupling capacitance (to adjacent wires), Ground capacitance (to substrate/layers), and Via resistance. Output formats: SPEF, DSPF, SBPF. Accuracy depends on extraction rules and technology modeling. Coupling capacitance is critical for crosstalk analysis. Post-layout STA uses extracted parasitics for signoff timing. Tools: Synopsys StarRC, Cadence Quantus.

Scan insertion replaces flip-flops with scan flip-flops having multiplexed inputs (functional data vs scan chain data). Scan chains connect flip-flops serially for shifting in test patterns and shifting out responses. Compression (DFTMAX, EDT) reduces tester data volume and test time: Decompressor expands compressed input to multiple scan chains, Compactor compresses multiple chain outputs into smaller signature, achieving 10-100x compression. Design flow: Insert scan, insert compression logic, verify scan connectivity, and generate ATPG patterns. Considerations: scan enable timing, test coverage targets, and chain balancing.

Crosstalk is unwanted coupling between adjacent signals via capacitance. Effects: Crosstalk delay (aggressor switching affects victim timing), Crosstalk noise (glitch on victim), and Functional failures. Analysis categorizes aggressor-victim pairs and checks timing impact and noise immunity. Mitigation: Increase spacing (routing rules for critical nets), Use shielding (grounded wires between sensitive signals), Minimize parallel run length, NDR (non-default routing rules) for critical nets, and Buffer insertion (reduce transition times). SI-aware routing and timing tools consider crosstalk during optimization.

Formal equivalence checking (FEC) mathematically proves two designs are functionally identical without simulation. Uses: RTL to gate-level (verify synthesis), Pre-CTS to post-CTS (verify clock tree), Pre-ECO to post-ECO (verify late changes), and Gate-level to gate-level (verify optimization). Tools map corresponding points (registers, I/O) and prove combinational logic between them is equivalent. Handles state mapping, phase mapping, and retiming. Advantages: exhaustive verification, faster than simulation for equivalence. FEC is essential for signoff quality assurance.

IR drop is voltage reduction across power distribution network due to resistance and current flow (V = I*R). Static IR: DC current through PDN resistance. Dynamic IR: Switching current causes transient voltage drop. Effects: Timing degradation (cells slower at lower voltage), functional failures (logic levels compromised), and reliability issues. Analysis: Vectorless (statistical switching activity) or vector-based (specific test patterns). Mitigation: Wider power straps, more vias, decoupling capacitors, and power mesh optimization. Signoff criteria: typically 5-10% VDD maximum drop.

Clock gating disables clock to idle flip-flops, eliminating switching power. Types: Latch-based (ICG - Integrated Clock Gating cell uses latch to avoid glitches), Latch-free (AND/OR gate, prone to glitches). Implementation: Synthesis tool identifies enable conditions, inserts gating cells, merges gates for efficiency. Considerations: Setup/hold timing of enable signal, gating cell latency, sequential clock gating (multi-cycle enable), and verification of clock gating coverage. Typical savings: 20-40% dynamic power. Clock gating is essential for low-power design alongside multi-Vt and power gating.

Placement positions standard cells to optimize timing, area, power, and routability. Objectives: Minimize total wirelength, Meet timing constraints, Reduce congestion, and Minimize power (short wires = less capacitance). Techniques: Global placement (approximate positions minimizing cost function), Detailed placement (legalize to rows, cell ordering optimization), and Incremental placement (post-route optimization). Timing-driven placement uses timing criticality to guide optimization. Congestion-driven placement spreads cells in dense regions. Modern tools use analytical and machine-learning approaches for optimization.

Multi-Vt uses cells with different threshold voltages: High-Vt (HVT): Lower leakage, slower, used in non-critical paths; Low-Vt (LVT): Higher leakage, faster, used in critical timing paths; Standard-Vt (SVT): Balance between speed and leakage. Design flow: Start with HVT, swap to LVT/SVT on timing-critical paths during optimization. Typically 60-80% HVT, rest LVT/SVT. Implementation through cell library variants. Trade-off: Each LVT cell may leak 10x more than HVT. Multi-Vt is fundamental for balancing performance and power in advanced nodes.

Global routing: Divides chip into global routing cells (GCells), plans rough wire paths, assigns nets to GCells without exact tracks, focuses on congestion management. Detailed routing: Routes nets on exact metal tracks within GCells, handles design rules (spacing, via rules), uses track assignment and maze routing algorithms. Routing layers: Lower metals for local connections, upper metals for global signals. Considerations: Antenna rules, via minimization, crosstalk, and timing. Modern routers are timing-aware and use multi-threaded algorithms for speed.

UVM (Universal Verification Methodology) is a SystemVerilog-based verification framework providing reusable, standardized testbench components. Key elements: uvm_driver (drives interface signals), uvm_monitor (observes interface), uvm_sequencer (generates transactions), uvm_scoreboard (checks correctness), uvm_agent (groups driver/monitor/sequencer), and uvm_env (top-level environment). Features: Factory pattern for configuration, TLM (Transaction Level Modeling) for communication, phases for synchronization, and register abstraction layer (RAL). UVM enables systematic coverage-driven verification with reusable, configurable testbenches.

Electromigration (EM) is metal atom movement due to electron momentum transfer in high-current-density wires, causing voids (open circuits) or hillocks (shorts). Affected by: Current density, temperature, wire material and structure. EM analysis compares current through wires against EM limits defined by foundry reliability models (typically for 10-year lifetime). Mitigation: Wider wires for high-current paths, proper via arrays, limit DC current density, and use Cu instead of Al. Signoff requires EM-clean designs. Also consider: ESD, hot carrier injection, and NBTI for reliability.

FSM encoding affects area, timing, and power. Binary encoding: minimum flip-flops (log2 N for N states), complex next-state logic. One-hot encoding: N flip-flops for N states, simple fast logic, larger area, preferred for FPGAs. Gray encoding: minimal bit transitions between adjacent states, good for low power and CDC. Enum encoding: compiler chooses, good readability. Synthesis directives or attributes guide encoding choice. One-hot typically faster but larger; binary denser but slower. Analysis should consider state machine size, performance requirements, and target technology.

Timing exceptions modify default timing constraints: False paths: Paths that never sensitize (e.g., static configuration, mutually exclusive modes), excluded from timing analysis. Multi-cycle paths: Paths intentionally requiring more than one clock cycle, setup/hold checked accordingly. Min/max delay: Specify specific delay ranges for paths. Clock groups: Define asynchronous clock relationships. Case analysis: Set specific values for mode-selection logic. Proper exception specification is critical for accurate timing; over-constrained designs waste effort, under-constrained miss violations. Document exceptions with justification.

Filler cells: Fill gaps between placed cells, provide continuous power/ground rails, and maintain manufacturing continuity (no isolated active regions). Types include: simple fillers, decoupling capacitor fillers (add decap), and metal-only fillers. Tap cells (well taps): Connect n-well and p-substrate to their respective supplies, prevent latch-up by maintaining proper well potentials. Placed at regular intervals (foundry-specified maximum distance, typically 20-30um). Both are inserted post-placement and are essential for DRC-clean, manufacturable, and reliable designs.

Voltage domain crossing occurs when signals pass between regions at different supply voltages. Level shifters convert voltage levels: Low-to-high shifter boosts voltage, High-to-low shifter reduces voltage (simpler). Isolation cells prevent floating or illegal values when power domain is off. Implementation: Insert level shifters at domain boundaries, use isolation for power-gated domains, consider timing impact of shifters, and verify correct shifter insertion. Special cells handle retention signals. UPF (Unified Power Format) specifies power intent for automated tool handling.

Assertions are formal statements about design behavior checked during simulation or formal verification. Types: Immediate assertions (checked instantaneously, like if statements), Concurrent assertions (check behavior over time using sequences/properties). SVA (SystemVerilog Assertions) constructs: property (temporal behavior), sequence (signal patterns), cover (coverage collection), and assume (constrain environment). Uses: Bug detection during simulation, formal property checking, and coverage measurement. Assertion-based verification catches bugs earlier, provides documentation, and enables formal verification integration.

Advanced node challenges: FinFET complexities (discrete width, self-heating, new layout rules), Interconnect dominance (wire delay exceeds gate delay, RC is limiting factor), Variability (local and global variation increases, OCV margins), Design rules (complex DFM rules, restrictive routing), Multiple patterning (SADP/SAQP, coloring constraints), IR drop and EM (thin wires, high current density), EUV lithography considerations, Reliability (BTI aging, hot carrier), and Power (leakage at subthreshold). Solutions include: advanced physical design techniques, machine-learning for optimization, signoff at many corners, and design-technology co-optimization.

OCV (On-Chip Variation) accounts for variations in nominally identical structures. Traditional OCV applies flat derating (e.g., +/- 5%) to all cells. AOCV (Advanced OCV) uses depth and distance-based derating: variation decreases with more stages (statistical averaging) and distance (spatial correlation). Tables specify derates based on path depth. POCV (Parametric OCV) is most accurate: uses statistical timing with cell-specific sigma values, computes path variation using SRSS (square root of sum of squares), provides realistic pessimism reduction. Modern signoff requires AOCV or POCV for reasonable margins while maintaining guardband.

Physical verification ensures layout is manufacturable and functional. DRC: geometry rules (width, spacing, enclosure, area). LVS: circuit connectivity matches schematic. ERC: electrical rules (floating gates, well connections). Antenna: progressive damage from plasma etching. DFM: yield-impacting patterns (via redundancy, wire widths). Signoff checks: Timing (STA at all corners), Power (IR drop, EM), Signal integrity (crosstalk, noise), and Physical (DRC, LVS, antenna, density). Foundry-specific checks using qualified tools (Calibre, IC Validator). Metal fill for density uniformity. Full signoff requires clean results from all checks.

Clock mesh distributes clock through grid structure instead of tree. Benefits: Lower skew (multiple paths average out variations), Better OCV tolerance, and Inherent redundancy. Design: Pre-mesh tree distributes clock to mesh vertices, mesh spreads clock across chip, taps from mesh to flip-flops. Challenges: Higher power (mesh constantly driven), complex analysis (multiple paths), and careful mesh design for balance. Hybrid approaches use mesh for critical regions, tree elsewhere. Analysis requires mesh-aware CTS tools and timing models. Used in high-performance processors where skew must be minimized despite large die sizes.

UPF (Unified Power Format) captures power intent in a technology-independent way. Key constructs: create_power_domain (define voltage domains), create_supply_port/net (power connections), set_isolation (floating output prevention), set_retention (state saving), add_power_state (operating modes), and create_pst (power state table). Verification: Power-aware simulation checks isolation/retention behavior, Formal verification proves power intent correctness, Physical implementation inserts special cells. Flow: RTL + UPF -> power-aware synthesis -> implementation -> signoff. UPF enables separation of power concerns from RTL, portability across tools, and consistent power verification.

Formal property verification (FPV) proves or disproves assertions mathematically. Effective application: Start with clear properties (from spec, safety requirements), Use good abstractions and constraints (environment assumptions), Employ decomposition (prove sub-properties, use assume-guarantee), Address capacity (bounded proofs, abstraction, blackboxing), and Iterate on failures (debug counterexamples, refine properties). Coverage: measure what properties verify, unreachable states, vacuous proofs. Combine with simulation: formal for control-intensive logic, simulation for data paths. FPV excels at: protocol verification, corner-case detection, and exhaustive verification of critical functions.

Advanced CTS techniques: Multi-source CTS (multiple clock entry points for lower skew/latency), Concurrent clock and data optimization (CCD, optimize together for useful skew), OCV-aware CTS (build trees considering variation), Mesh + tree hybrid (mesh for tight skew regions), Multi-corner CTS (optimize across corners simultaneously), Power-aware CTS (minimize buffer count and clock capacitance), and Blockage-aware routing. Implementation: Define clock routing non-default rules (NDRs), specify skew groups for timing-critical blocks, use clock tree exceptions for special handling. Balance trade-offs between power, skew, latency, and variation tolerance.

ESD (Electrostatic Discharge) protection prevents damage from transient high-voltage events. Protection networks: Primary clamp at I/O pad (large device to shunt current to supply rails), Secondary clamp near core (limits voltage), Rail clamps (between VDD and VSS for power rail events), and CDM protection (charged device model events). Design considerations: Fast turn-on (ns timescale), low on-resistance (limit voltage during event), no impact on normal operation (parasitic capacitance, leakage), and full-chip simulation. ESD models: HBM, MM, CDM with specified voltage levels. I/O libraries include ESD cells; custom I/O requires careful ESD design.

Timing ECO (Engineering Change Order) fixes timing violations post-implementation without full re-run. Methodology: Analyze timing reports to identify violations, determine fix type (sizing, buffering, VT swap, routing), Generate ECO netlist changes, Place ECO cells (incremental placement), Route ECO nets (incremental routing), and Verify no new violations introduced. Tools: Automated ECO (Genus ECO, IC Compiler) or manual with scripts. Considerations: Minimize changes for quick convergence, maintain placement legality, verify DRC/LVS after ECO, and iterate if needed. Late-stage ECOs are common for unexpected timing issues or last-minute changes.

Coverage-driven verification (CDV) uses coverage metrics to guide test creation and measure completeness. Coverage types: Code coverage (line, branch, toggle, FSM), Functional coverage (user-defined scenarios, cross-coverage), and Assertion coverage (property evaluation). Methodology: Define coverage model from spec, create constrained-random tests, run regressions collecting coverage, analyze holes, create directed tests for gaps, and iterate to closure (typically 95%+ targets). Tools: Coverage databases, merging, trending analysis. Coverage doesn't guarantee correctness but indicates unexplored areas. Complement with formal verification for completeness.

Low-power verification ensures correct behavior across power states. Techniques: Power-aware simulation (model power states, isolation, retention using UPF), Formal verification (check isolation assertion, state retention, level shifter presence), Static checks (UPF consistency, missing special cells), and Emulation (long power sequences at speed). Key scenarios: Power-up/down sequences, Isolation behavior (correct values when domain off), Retention (state preserved across power cycle), Level shifting (voltage domain crossing), and Wake-up latency. Verification at both RTL (UPF interpretation) and gate level (actual cells). PA-specific coverage metrics track power state transitions.

Yield enhancement addresses manufacturing defects. DFM (Design for Manufacturing): Redundant vias (increase via reliability), wire spreading/widening (improve lithography), recommended rules beyond minimum, density balancing, and litho-friendly design (avoid problematic patterns). Redundancy: Memory spare rows/columns, logic redundancy with repair. Test and repair: Built-in self-test (BIST), e-fuse for post-silicon repair, and adaptive voltage/frequency for marginal parts. Diagnosis: Failure analysis, defect learning, and yield modeling. Collaboration: Designer-foundry feedback loop for process-design co-optimization. Yield ramp requires iterative improvement through multiple factors.

Custom layout considerations: Transistor sizing (W/L for drive strength, leakage), Device matching (common-centroid for differential pairs, identical surroundings), Parasitics minimization (compact layout, avoid long diffusions), Well proximity effect (distance from well edge), Electromigration (wire and via sizing for current), Thermal effects (heat spreading, hot-spot avoidance), Substrate coupling (guard rings, isolation), and Latch-up prevention (proper well taps, spacing rules). Layout styles: Stick diagram planning, Euler path for optimal diffusion sharing. Design rules: minimum dimensions, recommended rules for yield. Verification: DRC, LVS, parasitic extraction, post-layout simulation.

Emulation and prototyping accelerate verification beyond simulation. Emulation: Custom hardware (Cadence Palladium, Synopsys ZeBu) running design at MHz speeds, supports hardware/software co-verification, transaction-based debug, and power analysis. FPGA prototyping: Design mapped to FPGA boards, runs at tens of MHz, good for software development and system validation. Use cases: Boot operating systems, run real workloads, stress testing, and performance validation. Tradeoffs: Emulation offers better debug and flexibility, prototyping offers speed and lower cost. Both complement simulation for complete verification coverage.

3D IC stacks multiple dies or layers for increased functionality and reduced footprint. Challenges: TSV (Through-Silicon Via) design (TSV parasitics, keep-out zones, stress effects), Thermal management (power density, hot spots, limited heat paths), Power delivery (distributed PDN across tiers), Clock distribution (skew across dies), Testing (pre-bond, mid-bond, post-bond test strategies), Yield (compound yield of multiple dies), Design tools (3D-aware floor planning, thermal-aware placement), and Known-good-die selection. Benefits include: shorter interconnects, heterogeneous integration (logic + memory), and smaller form factor. Active area for research and advanced packaging development.