What is the RTL design flow in VLSI?

RTL (Register Transfer Level) design flow: 1) Specification - define functionality, 2) RTL coding - write Verilog/VHDL describing registers and combinational logic, 3) Functional verification - simulate to verify correctness, 4) Synthesis - convert RTL to gate-level netlist, 5) Static timing analysis - verify timing requirements, 6) Physical design - place and route, 7) Sign-off verification - final timing, power, DRC/LVS checks. This flow transforms behavioral description to manufacturable layout through automated tools while ensuring functional and timing correctness.