What are setup time and hold time in digital circuits?

Setup time (Tsu) is the minimum time data must be stable before the clock edge for reliable capture. Hold time (Th) is the minimum time data must remain stable after the clock edge. Violating setup time causes incorrect data capture; violating hold time causes the new data to corrupt the just-captured value. These timing constraints arise from flip-flop internal structure (propagation through latches). Static timing analysis verifies all paths meet setup and hold requirements under worst-case conditions (PVT corners).