What are key considerations in custom CMOS layout design?

Custom layout considerations: Transistor sizing (W/L for drive strength, leakage), Device matching (common-centroid for differential pairs, identical surroundings), Parasitics minimization (compact layout, avoid long diffusions), Well proximity effect (distance from well edge), Electromigration (wire and via sizing for current), Thermal effects (heat spreading, hot-spot avoidance), Substrate coupling (guard rings, isolation), and Latch-up prevention (proper well taps, spacing rules). Layout styles: Stick diagram planning, Euler path for optimal diffusion sharing. Design rules: minimum dimensions, recommended rules for yield. Verification: DRC, LVS, parasitic extraction, post-layout simulation.