What techniques are used for yield enhancement in VLSI?

Yield enhancement addresses manufacturing defects. DFM (Design for Manufacturing): Redundant vias (increase via reliability), wire spreading/widening (improve lithography), recommended rules beyond minimum, density balancing, and litho-friendly design (avoid problematic patterns). Redundancy: Memory spare rows/columns, logic redundancy with repair. Test and repair: Built-in self-test (BIST), e-fuse for post-silicon repair, and adaptive voltage/frequency for marginal parts. Diagnosis: Failure analysis, defect learning, and yield modeling. Collaboration: Designer-foundry feedback loop for process-design co-optimization. Yield ramp requires iterative improvement through multiple factors.