How do you verify low-power design implementations?

Low-power verification ensures correct behavior across power states. Techniques: Power-aware simulation (model power states, isolation, retention using UPF), Formal verification (check isolation assertion, state retention, level shifter presence), Static checks (UPF consistency, missing special cells), and Emulation (long power sequences at speed). Key scenarios: Power-up/down sequences, Isolation behavior (correct values when domain off), Retention (state preserved across power cycle), Level shifting (voltage domain crossing), and Wake-up latency. Verification at both RTL (UPF interpretation) and gate level (actual cells). PA-specific coverage metrics track power state transitions.