Scan Insertion and Compression | VLSI Interview | Skill-Lync Resources
Medium VLSI Design Verification

How does scan insertion and compression work for DFT?

Answer

Scan insertion replaces flip-flops with scan flip-flops having multiplexed inputs (functional data vs scan chain data). Scan chains connect flip-flops serially for shifting in test patterns and shifting out responses. Compression (DFTMAX, EDT) reduces tester data volume and test time: Decompressor expands compressed input to multiple scan chains, Compactor compresses multiple chain outputs into smaller signature, achieving 10-100x compression. Design flow: Insert scan, insert compression logic, verify scan connectivity, and generate ATPG patterns. Considerations: scan enable timing, test coverage targets, and chain balancing.

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