What is parasitic extraction and why is it important?

Parasitic extraction computes resistance (R) and capacitance (C) values from physical layout geometry for accurate timing, power, and signal integrity analysis. Extracts: Wire resistance (length, width, sheet resistance), Coupling capacitance (to adjacent wires), Ground capacitance (to substrate/layers), and Via resistance. Output formats: SPEF, DSPF, SBPF. Accuracy depends on extraction rules and technology modeling. Coupling capacitance is critical for crosstalk analysis. Post-layout STA uses extracted parasitics for signoff timing. Tools: Synopsys StarRC, Cadence Quantus.