How is power gating implemented in VLSI?

Power gating switches off unused blocks to eliminate leakage. Implementation: Sleep transistors (high-Vt PMOS headers or NMOS footers) connect block to supply, Isolation cells prevent floating outputs from corrupting always-on logic, Retention flip-flops save state before power-down, Level shifters handle voltage differences, and Power control unit sequences on/off events. Design considerations: rush current during wake-up (inrush), wake-up latency, area overhead (10-15%), and IR drop through sleep transistors. Coarse-grained (full blocks) is simpler; fine-grained adds overhead but more flexibility.