What is involved in physical verification and signoff?

Physical verification ensures layout is manufacturable and functional. DRC: geometry rules (width, spacing, enclosure, area). LVS: circuit connectivity matches schematic. ERC: electrical rules (floating gates, well connections). Antenna: progressive damage from plasma etching. DFM: yield-impacting patterns (via redundancy, wire widths). Signoff checks: Timing (STA at all corners), Power (IR drop, EM), Signal integrity (crosstalk, noise), and Physical (DRC, LVS, antenna, density). Foundry-specific checks using qualified tools (Calibre, IC Validator). Metal fill for density uniformity. Full signoff requires clean results from all checks.