How do you design ESD protection for I/O pads?

ESD (Electrostatic Discharge) protection prevents damage from transient high-voltage events. Protection networks: Primary clamp at I/O pad (large device to shunt current to supply rails), Secondary clamp near core (limits voltage), Rail clamps (between VDD and VSS for power rail events), and CDM protection (charged device model events). Design considerations: Fast turn-on (ns timescale), low on-resistance (limit voltage during event), no impact on normal operation (parasitic capacitance, leakage), and full-chip simulation. ESD models: HBM, MM, CDM with specified voltage levels. I/O libraries include ESD cells; custom I/O requires careful ESD design.