What is the methodology for timing ECO in physical design?

Timing ECO (Engineering Change Order) fixes timing violations post-implementation without full re-run. Methodology: Analyze timing reports to identify violations, determine fix type (sizing, buffering, VT swap, routing), Generate ECO netlist changes, Place ECO cells (incremental placement), Route ECO nets (incremental routing), and Verify no new violations introduced. Tools: Automated ECO (Genus ECO, IC Compiler) or manual with scripts. Considerations: Minimize changes for quick convergence, maintain placement legality, verify DRC/LVS after ECO, and iterate if needed. Late-stage ECOs are common for unexpected timing issues or last-minute changes.