What are timing exceptions and how are they used in STA?

Timing exceptions modify default timing constraints: False paths: Paths that never sensitize (e.g., static configuration, mutually exclusive modes), excluded from timing analysis. Multi-cycle paths: Paths intentionally requiring more than one clock cycle, setup/hold checked accordingly. Min/max delay: Specify specific delay ranges for paths. Clock groups: Define asynchronous clock relationships. Case analysis: Set specific values for mode-selection logic. Proper exception specification is critical for accurate timing; over-constrained designs waste effort, under-constrained miss violations. Document exceptions with justification.