What is UVM and how is it used for verification?

UVM (Universal Verification Methodology) is a SystemVerilog-based verification framework providing reusable, standardized testbench components. Key elements: uvm_driver (drives interface signals), uvm_monitor (observes interface), uvm_sequencer (generates transactions), uvm_scoreboard (checks correctness), uvm_agent (groups driver/monitor/sequencer), and uvm_env (top-level environment). Features: Factory pattern for configuration, TLM (Transaction Level Modeling) for communication, phases for synchronization, and register abstraction layer (RAL). UVM enables systematic coverage-driven verification with reusable, configurable testbenches.