What is the difference between static and dynamic power in CMOS?

Dynamic power is consumed during switching: P_dyn = alpha * C * V^2 * f, where alpha is activity factor, C is load capacitance, V is supply voltage, and f is frequency. It dominates in older technologies. Static power (leakage) flows when circuits are idle, mainly from subthreshold leakage, gate leakage, and junction leakage. It becomes significant in advanced nodes (below 90nm). Total power = dynamic + static. Modern low-power design addresses both through techniques like clock gating (dynamic) and power gating (static).