What are the key challenges in designing at advanced technology nodes (7nm and below)?

Advanced node challenges: FinFET complexities (discrete width, self-heating, new layout rules), Interconnect dominance (wire delay exceeds gate delay, RC is limiting factor), Variability (local and global variation increases, OCV margins), Design rules (complex DFM rules, restrictive routing), Multiple patterning (SADP/SAQP, coloring constraints), IR drop and EM (thin wires, high current density), EUV lithography considerations, Reliability (BTI aging, hot carrier), and Power (leakage at subthreshold). Solutions include: advanced physical design techniques, machine-learning for optimization, signoff at many corners, and design-technology co-optimization.