How are assertions used in VLSI verification?

Assertions are formal statements about design behavior checked during simulation or formal verification. Types: Immediate assertions (checked instantaneously, like if statements), Concurrent assertions (check behavior over time using sequences/properties). SVA (SystemVerilog Assertions) constructs: property (temporal behavior), sequence (signal patterns), cover (coverage collection), and assume (constrain environment). Uses: Bug detection during simulation, formal property checking, and coverage measurement. Assertion-based verification catches bugs earlier, provides documentation, and enables formal verification integration.