What is logic synthesis in VLSI design?

Logic synthesis transforms RTL description (Verilog/VHDL) into gate-level netlist using cells from a technology library. The synthesizer optimizes for area, timing, and power while meeting constraints. Steps: RTL parsing, technology-independent optimization (Boolean minimization, common subexpression elimination), technology mapping (mapping to library cells), and timing optimization (buffer insertion, cell sizing). Key inputs: RTL code, constraints (clock, I/O timing), and technology library. Output: Netlist in standard format (Verilog, DEF). Modern tools: Synopsys Design Compiler, Cadence Genus.