How do you handle clock domain crossing in VLSI design?

CDC handling involves: Synchronizers (2FF for single-bit, multi-bit needs special treatment), Gray coding (for counters crossing domains), Asynchronous FIFOs (for data transfers), Handshake protocols (request/acknowledge), and Pulse synchronizers (for single-cycle signals). Verification: CDC analysis tools (Spyglass CDC, Conformal) detect missing synchronizers, reconvergence issues, and multi-bit signal problems. Design guidelines: minimize CDC signals, use established crossing circuits, document intentional exceptions, and verify MTBF requirements. Metastability is inherent; synchronizers reduce failure probability to acceptable levels.