What are common techniques for achieving timing closure?

Timing closure techniques: Gate sizing (upsize critical path cells, downsize non-critical for area), Buffer insertion (reduce load, manage slew), Logic restructuring (parallelize logic, reduce depth), Useful skew (intentionally skew clock to borrow time), Layer assignment (fast metal layers for critical nets), Placement optimization (move cells closer), and VT swapping (low-Vt for critical paths). Process involves iterative refinement, using timing reports to identify violations and applying incremental fixes. ECO (Engineering Change Order) enables late-stage targeted fixes.